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The revised version of the AWBS-1000 modem solution. The AWBS-1100 modem solution supports the 3GPP (Third Generation Partnership Project) standards based on FDD mode release 99 (2001.6.).



The AWBS-1100 modem solution provides the data throughput of up to 2 Megabits per second (Mbps) by using the multi-code transmission.
The AWBS-1100 modem solution supports 16 simultaneous voice and/or data channels. The internal resources of the AWBS-1100 have 16 uplink channel resources and 24 downlink channel resources.
Each channel resources are configured to any physical channels simultaneously.
Alogics' modem solution is implemented by using the AWBS-1100 ASIC (Application Specific Integrated Circuit) and a DSP (Digital Signal Processor) like Texas Instruments' TMS320C6416.
Generally the multiple modem solutions are located in a channel card to increase the channel capacity and the performance.
So the Daisy chain (link) combining is provided in the AWBS-1100 modem solution for the serial concatenation of multiple transmitters.





Standard Compliance
FDD mode 3GPP Rel.99 (2001.06)
Data Throughput
Maximum 2 Mbps in both uplink and downlink
Using the multi-code transmission
Simultaneous Voice/Data Channels
Number of channel : 16
Tx Antenna Interface
Number of transmit antenna : 12
Two antennas per a sector
Six sectors configuration
Configurable Channel Resources
Uplink physical channels : 16
Downlink physical channels : 24
Independently configurable to any physical channels
Transmit Diversity
STTD, TSTD and Closed loop mode
Handoff Support
Six simultaneous transmit sectors for softer handover mode
SSDT in soft handover mode
Signal Interface at Receiver
Eight times oversampling rate (chipx8)
Four bits sample per each I and Q
Signal Interface at Transmitter
Chip rate sample
16 bits sample per each I and Q
One parity bit per a sample
Daisy Chain(Link) Combining
For serial concatenation of multiple transmitters
Digital Signal Processor (DSP) Interface
compatible with Texas Instruments' DSP (6416)
64-bit interface
Up to 60 MHz per access
Two General Purpose I/O (GPIO) Pins
492-pin Ball Grid Array (BGA) Package
0.18§­ CMOS Technology
3.3V I/O, 1.8V Internal